1. Field of the Invention
The present invention relates to a method for mounting anisotropically-shaped members.
2. Description of the Related Art
For the fabrication of thin-film transistors (TFTs) used for flat panel displays such as active-matrix liquid crystal display devices and organic electroluminescence display devices, and transistors used for large-scale integrated (LSI) circuits, a micro fabrication process is employed that processes a thin-film material by vacuum thin film techniques and photolithography techniques. With the recent trend for large-screen display devices that have been pervasive these days, the display device in particular requires large manufacturing facilities such as the exposure equipment used for photolithography processes. This has necessitated large investments on plants and facilities. The cost of photomask has been increasing as well.
With the recent advance in nanotechnology, various ideas have been put forth and research and development has been active on electronic devices using, for example, pillar-like members having a diameter smaller than several hundred nanometers (may be referred to as “nanomembers” hereinafter). The pillar-like nanomembers include needle-like nanoparticles, for example, such as carbon nanotubes and semiconductor nanowires. An application of such nanomembers for an electronic device is described, for example, by D. Wang, et al., “Germanium nanowire field-effect transistors with SiO2 and high-k HfO2 gate dielectric”, Appl. Phys. Lett. Vol. 83, pp. 2432, 2003, which describes operations of field-effect transistors (may be referred to as FETs) with semiconductor nanowires at ordinary temperature. The field-effect transistors using such nanomembers are fabricated by a coating technique, and as such the fabrication does not require techniques using various kinds of large-scale vacuum equipment as required in conventional thin film techniques. Conceivably, the technique disclosed in this publication has many advantages, including cost reduction.
However, in order to realize transistor characteristics using nanomembers, the nanomembers need to be disposed in predetermined microscopic regions in a uniaxial orientation. This is necessary because field-effect transistors can be realized by forming a source electrode and a drain electrode at the both ends of each pillar-like nanomember that has been disposed in a uniaxial orientation. One of the big challenges, in order to fabricate the field-effect transistors of a coating type using nanomembers, is therefore the precise control of the orientation and position of the nanomembers in mounting the nanomembers on the substrate. For example, as a method of controlling the orientation and position of the nanomembers, there has been reported a method in which a mold made of polydimethylsiloxane (PDMS) with large numbers of grooves is brought into contact with a substrate surface to form channels for flowing a liquid, and a liquid in which the nanomembers are dispersed is flown through the channels to coat the substrate with pillar-like nanomembers in a particular orientation (referred to as “flow method” hereinafter) (see U.S. Pat. No. 6,872,645; Y. Huang, et al., “Directed Assembly of One-Dimensional Nanostructures into Functional Networks,” Science vol. 291, pp. 630, 2001).
In another method for disposing and orienting the nanomembers on a substrate, a transfer sheet (donor sheet) is used on which the nanomembers have been oriented and disposed, and the nanomembers are transferred to a substrate that has been provided with an adhesive layer (buffer layer), as disclosed, for example, in JP2005-244240A. In this method, the transfer sheet is temporarily bonded to the adhesive layer of the substrate, and the patterns to be transferred are heated by irradiation of a laser beam to bond the nanomembers formed on the transfer sheet to the adhesive layer (transfer of the nanomembers to the substrate). The transfer sheet is formed of a transfer layer (a layer of nanomembers to be transferred) and an underlayer (a film holding the transfer layer). The underlayer includes a film whose adhesion deteriorates by the heat of a laser beam.
Meanwhile, active-matrix liquid crystal display devices and organic electroluminescence display devices are formed on a glass substrate. The pixels disposed in a matrix on the substrate are controlled by the transistors provided in the vicinity of the pixels. With current technology, however, crystalline semiconductor transistors cannot be formed on the glass substrate, and for this reason FETs using an amorphous silicon or polysilicon thin film have been used for the control of the pixels. The amorphous silicon or polysilicon thin film has the advantage that it can be formed on a large-area substrate at low cost; however, its smaller mobility compared with crystalline silicon has prevented them from operating at high speed. To overcome such a problem, there have been proposed techniques in which the FETs are first fabricated on a silicon wafer of crystalline silicon in a large quantity and then cut into individual pieces to be disposed on a substrate that has been provided with openings of a size for setting the FETs (see U.S. Pat. No. 6,417,025; JP2003-5212A; Information Display, p. 12-16, 1999).
However, when the conventional flow method is used to control the orientation and position of the pillar-like nanomembers in mounting these members on a substrate, there are difficulties in stably orienting and positioning the members.
Further, in the method of disposing the nanomembers by transferring the nanomembers onto the substrate provided with the adhesive layer, the nanomembers are anchored on the adhesive layer in the orientation the nanomembers are oriented on the transfer sheet. In placing the nanomembers on the transfer sheet, while the nanomembers can be aligned substantially parallel to one another along the longitudinal direction, it is very difficult to align the nanomembers with the ends of the nanomembers lined up. For this reason, it has been difficult with this method to dispose the nanomembers on the substrate substantially parallel to one another along the longitudinal direction with the ends of the nanomembers lined up in substantially in line. Another drawback of this method in that, because the adhesive layer is used, there are cases where the nanomembers are buried in the adhesive layer, which may lead to problems such as failing to realize transistor characteristics.
When conventional methods are used to dispose fabricated members such as FETs and a silicon sheet on a substrate, a problem arises that the FETs or silicon sheet cannot be oriented and disposed accurately in predetermined positions. Because the probability of accurately disposing the members on the substrate is small, larger numbers of members need to be prepared than necessary. This increases the manufacturing cost.